1. Field of the Invention
The present invention relates to a serial I/O incorporated semiconductor device provided with a serial I/O having a plurality of transmitting pins and a plurality of receiving pins.
2. Description of the Prior Art
FIG. 11 is a configuration of a conventional serial I/O incorporated semiconductor device. In FIG. 11, the semiconductor device is provided with only one channel. In FIG. 11, reference numeral 101 indicates an I/O incorporated semiconductor device and 102 indicates a transmitting pin for outputting serial transmit data. 103 indicates a receiving pin for inputting serial received data and 104 indicates a transmitting unit, 105 indicates a receiving unit, 106 indicates a CPU, and 107 indicates a data bus.
In the transmitting unit 104, 111 indicates a transmission shift register for outputting written received data from the transmitting pin 102 and 112 indicates a transmission completion detection circuit for detecting normal completion of transmission of the transmit data 113 indicates a transmission completion flag set to have a predetermined value by the transmission completion detection circuit 112 that has detected normal completion of data transmission.
In the receiving unit 105, 121 indicates a receiving shift register in which received data entered to the receiving pin 103 is written. 122 is a reception completion detection circuit for detecting normal completion of data receiving. 123 indicates a reception completion flag set to have a predetermined value by the reception completion detection circuit 122 that has detected normal completion of data receiving. 124 is a receiving error detection circuit for detecting unusual completion of data receiving. 125 indicates a receiving error flag set to have a predetermined value by the receiving error detection circuit 124 that has detected unusual completion of data receiving. 126 indicates an OR circuit having one input to which the value from the reception completion flag 123 is input and the other input to which the value from the receiving error flag 125 is input respectively. The OR circuit is also provided with an output pin for supplying its value to the CPU 106.
Hereunder, the operation of the I/O incorporated semiconductor device will be explained.
When transmitting transmit data, the transmit data is written in the transmission shift register 111. Then, the transmit data is output from the transmitting pin 102.
When the transmit data is transmitted completely, the transmission completion detection circuit 112 detects the normal completion of the transmission and the transmission completion flag 113 is set to a value "1".
Thereafter, the value of the transmission completion flag 113 is supplied to the CPU 106 as a transmission interruption signal. Receiving the signal, the CPU 106 executes a transmission completion interruption program to check the value of the transmission completion flag 113 and recognizes the normal transmission of the transmit data.
When receiving data, the received data entered to the receiving pin 103 is written in the receiving shift register 121.
When the received data is received normally, the reception completion detection circuit 122 detects the normal completion of reception of the received data and the reception completion flag 123 is set to a value "1". On the other hand, when the received data is not received normally, the receiving error detection circuit 124 detects the unusual completion of receiving and the receiving error flag 125 is set to "1".
The value "1" set in either the reception completion flag 123 or the receiving error flag 125 is supplied to the CPU 106 as a reception interrupt signal. Receiving the signal, the CPU 106 executes a receiving interruption program to check the values of the reception completion flag 123 and the receiving error flag 125. If "1" is set in the reception completion flag 123, the CPU executes a normal processing. If "1" is set in the receiving error flag 125, the CPU executes an error processing.
Because the conventional serial I/O incorporated semiconductor device provided with one channel is constructed described above, the conventional serial I/O incorporated semiconductor, when being provided with a plurality of channels, needed transmitting units and receiving units as many as the number of channels. Consequently, the conventional I/O incorporated semiconductor device provided with a plurality of channels is confronted with a problem that the device becomes very large in size.